Various types of memories have been developed in the past as electronic memory media for computers and similar systems. Such memories include electrically erasable programmable read only memory (EEPROM) and electrically programmable read only memory (EPROM). Each type of memory had advantages and disadvantages. EEPROM can be easily erased without extra exterior equipment but with reduced data storage density, lower speed, and higher cost. EPROM, in contrast, is less expensive and has greater density but lack erasability.
A newer type of memory called “Flash” EEPROM, or Flash memory, has become extremely popular because it combines the advantages of the high density and low cost of EPROM with the electrical erasability of EEPROM. Flash memory can be rewritten and can hold its contents without power. It is used in many portable electronic products, such as cell phones, portable computers, voice recorders, etc. as well as in many larger electronic systems, such as cars, planes, industrial control systems, etc.
In Flash memory, bits of information are programmed individually as in the older types of memory, such as dynamic random access memory (DRAM) and static random access memory (SRAM) memory chips. However, in DRAMs and SRAMs where individual bits can be erased one at a time, Flash memory must currently be erased in fixed multi-bit blocks or sectors.
Conventionally, Flash memory is constructed of many Flash memory cells where a single bit is stored in each memory cell and the cells are programmed by hot electron injection and erased by Fowler-Nordheim tunneling. However, increased market demand has driven the development of Flash memory cells to increase both the speed and the density. Newer Flash memory cells have been developed that allow more than a single bit to be stored in each cell.
One memory cell structure involves the storage of more than one level of charge to be stored in a memory cell with each level representative of a bit. This structure is referred to as a multi-level storage (MLS) architecture. Unfortunately, this structure inherently requires a great deal of precision in both programming and reading the differences in the levels to be able to distinguish the bits. If a memory cell using the MLS architecture is overcharged, even by a small amount, the only way to correct the bit error would be to erase the memory cell and totally reprogram the memory cell. The need in the MLS architecture to precisely control the amount of charge in a memory cell while programming also makes the technology slower and the data less reliable. It also takes longer to access or “read” precise amounts of charge. Thus, both speed and reliability are sacrificed in order to improve memory cell density.
An even newer technology allowing multiple bits to be stored in a single cell has been developed, i.e., “MirrorBit®” Flash memory. In this technology, a memory cell is essentially split into two identical (mirrored) parts, each of which is formulated for storing one of two independent bits. Each MirrorBit Flash memory cell, like a traditional Flash cell, has a gate with a source and a drain. However, unlike a traditional Flash cell in which the source is always connected to an electrical source and the drain is always connected to an electrical drain, each MirrorBit Flash memory cell can have the connections of the source and drain reversed during operation to permit the storing of two bits.
The MirrorBit Flash memory cell has a semiconductor substrate with implanted conductive bitlines. A multilayer storage layer, referred to as a “charge-trapping dielectric layer”, is formed over the semiconductor substrate. The charge-trapping dielectric layer can generally be composed of three separate layers: a tunneling layer, a charge-trapping layer, and a second insulating layer. Wordlines are formed over the charge-trapping dielectric layer perpendicular in the bitlines. Programming circuitry controls two bits per cell by applying a signal to the wordline, which acts as a control date, and changing bitline connections such that one bit is stored by source and drain being connected in one arrangement and a complementary bit is stored by the source and drain being interchanged in another arrangement.
Programming of the cell is accomplished in one direction and reading is accomplished in a direction opposite that in which it is programmed.
The SONOS type memory devices can be formed in the following manner. In Mitchell et al., U.S. Pat. No. 5,168,334, EEPROM memory cells are formed with buried bitlines. The buried bitlines and bitline oxides are formed in the core region of the substrate prior to formation of the ONO dielectric. Alternatively, Mitchell et al. forms EEPROM memory cells by forming an ONO dielectric, depositing polysilicon over the ONO dielectric, patterning the polysilicon, forming the buried bitlines, and removing the ONO dielectric covering the bitlines. In Eitan, U.S. Pat. No. 5,966,603, after an ONO dielectric is formed over the substrate, a bitline mask is patterned over the ONO dielectric in the core while completely covering the periphery. Portions of the top oxide and nitride layers left exposed by the bitline mask are etched/removed. The bitlines are implanted, and then the bitline oxides are formed over the bitlines. In Eitan et al., PCT International Publication No. WO 99/60631, memory cells are formed by forming an ONO dielectric over a substrate. Next, a bitline mask with openings for the bitlines is formed over the ONO dielectric. Then, the top oxide and nitride layers left exposed by the bitline mask are etched/removed. The bitlines are implanted, the bitline mask is removed, the exposed portions of the bottom oxide of the ONO dielectric are removed, gate oxides are grown, including thick oxide growth over the bitlines, and polysilicon gates and wordlines are formed.
The SONOS type FLASH memory cell structure has been described as a two-transistor cell or two-bit per cell memory device. If a multi-level is used, then four or more bits per cell can be accomplished. Multi-bit cells enable SONOS type memory devices to have the advantage over others in facilitating the continuing trend of increasing the amount of information held/processed on an integrated circuit chip. Additionally, the manufacture of both floating gate FLASH memory type devices and SONOS type memory devices continue to scale the floating gate FLASH memory cells and the SONOS type FLASH memory cells in order to increase the number of devices formed on a chip that forms an integrated circuit. Given the continuing trend towards miniaturization and increased integration of devices on an integrated circuit chip, efficient utilization of space is of increasing importance.
Unfortunately, as the channel size is decreased, there is potential for the semiconductor device to be affected by the short channel effect. The short channel effect is a decrease in the effective channel length, often represented as Leff. Decreasing the effective channel length can result in an undesirable off-state current passing between the buried bitlines, much like the off-state current in MOS transistors. Thus, the undesirable current passing between the buried bitlines limits the further scaling of non-volatile memory devices.
Additionally, in the manufacture of semiconductor devices, there are multiple high temperature cycles (thermal cycles) that may adversely increase off-state leakage current by increasing diffusion of the buried bitlines and reducing the effective change length.
Therefore, there is a strong need in the art for non-volatile memory devices with buried bitlines that inhibit the off-state leakage current between the buried bitlines. Additionally, there is a need in the art for buried bitlines that allow further scaling of non-volatile memory devices. Further, there is a need to apply such buried bitlines to other arrays of semiconductor devices.